The Greening and Hardening of Dark Silicon

The Greening and Hardening of Dark Silicon

July 17, 2014


Karlsruhe, Germany


Sri Parameswaran


The Greening and Hardening of Dark Silicon
A Low Power and a Reliability Perspective


A sea of processors is expected to soon dominate the design horizon of chips. By 2020 the number of cores is anticipated to increase by thirty fold. While the processor size shrinks to 1/30th of what it is today, the power consumption will still be 1/8th of what it is today. This leads to a power density increase which cannot be sustained. Thus much of the chip will be switched off so the chip itself can be powered without self-destructing. In fact up to 92% of the chip is expected to be dark in the foreseeable future. In this seminar we will examine techniques to exploit dark silicon to reduce power and improve performance. Two techniques in particular will be described. The first is a novel network on chip technique which describes how it can be created such that energy can be saved, with little loss of performance. The second is a cache architecture method which can both improve performance and reduce power consumption. We will examine how reliability is usually calculated in systems where redundancy is prevalent. Particularly in systems with dark silicon, redundancy is possible. We examine the correctness of all the assumptions, and compare it with the financial markets.

Short Bio

Sri Parameswaran is a Professor in the School of Computer Science and Engineering at the University of New South Wales, Australia. He serves as the Postgraduate Research and Scholarship Co-ordinator, and is an active researcher. He has served on the Technical Program Committee of numerous ACM/IEEE International Conferences, such as Design Automation Conference (DAC), Design and Test in Europe (DATE), the International Conference on Computer Aided Design (ICCAD), the International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS, as TPC chair), and the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES). He is an associate editor of IEEE Transactions on Computer Aided Design (TCAD), and was an associate editor of the ACM Transactions on Embedded Computing Systems, and the EURASIP Journal on Embedded Systems.