Special Session at DATE 2014
Connecting different worlds – technology abstraction for reliability-aware design and test
March 27, 2014
Ulf Schlichtmann, Andreas Herkersdorf
The rapid shrinking of device geometries in the nanometer regime requires new technology-aware design methodologies. These must be able to evaluate the resilience of the circuit throughout all System on chip (Soc) abstraction levels. to successfully guide design decisions at the system level, reliability models, which abstract technology information, are required to identify those parts of the system where additional protection in the form of hardware or software countermeasures is most effective. Interfaces such as the presented resilience articulation point (rap ) or the reliability Interchange Information Format (rIIF) are required to enable eDa-assisted analysis and propagation of reliability information. the models are discussed from different perspectives, such as design and test.