International Workshop on Hardware/Software Techniques for Cross-Layer Resiliency

International Workshop on Hardware/Software Techniques for Cross-Layer Resiliency
Venue:

International Conference on Computer-Aided Design (ICCAD)

Place:

San Jose, USA 

Date:

November 8, 2012

Year:

2012 

Program Chair:

Vikas Chandra, 
Nikil Dutt, 
Siddharth Garg, 
Brett Meyer, 
Sani Nassif,
Hiren Patel,
Mehdi Tahoori

Links:Reliabilty Workshop

Topics

Improvements in chip manufacturing technology have propelled an astonishing growth of embedded systems which are integrated into our daily lives. However, this trend is facing serious challenges, both at device and system levels. At the device level, as the minimum feature size continues to shrink, a host of vulnerabilities influence the robustness, reliability, and availability of embedded and critical systems. Some of these factors are caused by the stochastic nature of the nanoscale manufacturing process (e.g., process variability, sub-wavelength lithographic inaccuracies), while other factors appear because of high frequencies and nanoscale features (e.g. RLC noise, on-chip temperature variation, increased sensitivity to radiation and transistor aging). At the other end of the spectrum, embedded systems are seeing a tremendous increase in software content. Whereas traditional software design paradigms have assumed that the underlying hardware is fully predictable and error-free, there is now a critical need to build a software stack that is responsive to variations, and resilient against emerging vulnerabilities in the underlying hardware.

The objective of this workshop is to bring the attention of design automation community to the multilevel reliability challenges and solutions and possible paradigm shift to consider reliability throughout the design flow, from devices to systems and applications. This workshop will focus on innovative device- level, hardware (circuit and micro-architecture level) and software (application, operating system and compiler level) solutions for fault detection and recovery in multi-processor system-on-chip (MPSoC) platforms, as also on solutions for emerging applications and platforms that are inherently forgiving of errors in the computation and communication of data. In addition, this workshop tries to synchronize various existing coordinated research programs on dependability which are currently underway in Europe, Asia, and USA to deal with multi-level reliability challenges.