Design for Reliability in the Nano-CMOS Era: New Holistic Methodologies for Reliability Modeling and Optimization

24th Asia and South Pacific Design Automation Conference (ASP-DAC 2019)

January 21, 2019

Hussam Amrouch, et al.

Hussam Amrouch, Sheldon Tan

Reliability has become a significant challenge for design of current nanometer integrated circuits (ICs). Long-term reliability degradation caused by aging effects are becoming limiting constraints in emerging computing and communication platforms due to increased failure rates from the continuous transistor scaling, increasing process variations and aggressive power reductions. Reliability problems will get worse as future chips will show signs of aging much faster than the previous generations. Despite aging occurs at the physical level, workloads at the system level play a major role in stimulating the underlying mechanisms of aging. Therefore, holistic solutions in which the physical effects are linked with and abstracted all the way up to the system level become necessary for mitigating the looming reliability crisis.
The motivation of this tutorial is to understand the newest research results in reliability from ground up in which both Bias Temperature Instability (BTI) and Electromigration (EM), which are the key aging mechanisms in transistors and interconnect wires, are jointly covered. Intended audiences are circuit- and system- level designers who investigate reliability aspects in embedded systems.

Tokyo Odaiba Waterfront, Japan

http://www.aspdac.com/aspdac2019/tutorial