On the Generation of Small (Compact) Fault Detection Test Sets
May 30, 2014
Sudhakar M. Reddy
Test of manufactured VLSI circuits is essential to insure reliability of systems using the circuits. A substantial portion of the cost of VLSI circuits is attributable to cost of testing. The major component of the cost of testing is the cost of applying appropriate tests to detect manufacturing defects. This cost directly depends on the number of tests that need to be used to detect the defects. Tests used are derived by EDA tools called Automatic Test Pattern Generators (ATPGs) typically using, what are called, fault models to facilitate generation of tests that are effective in detecting the presence of defects in manufactured circuits. Generation of a set of tests of minimal size to detect all modeled faults is a challenging problem which has been investigated extensively over the last two plus decades. In collaboration with a commercial R&D group we have recently developed new methods to guide test generation procedures to achieve substantial reductions in the size of fault detection test sets. Details of these methods together with results on large industrial designs and comparison with the results using a state of the art commercial ATPG will be presented in this talk.
Professor Sudhakar M. Reddy received the B.Sc. degree in Physics and the B.E. degree in Electronic Communications Engineering (ECE) from Osmania University, Hyderabad, the M.E. degree in ECE from the Indian Institute of Science, Bangalore, India, and the Ph.D. degree from the University of Iowa, Iowa City, Iowa. He joined the faculty of the Department of Electrical and Computer Engineering at the University of Iowa in 1968 where he is currently a University of Iowa Foundation Distinguished Professor of ECE. He served as the Department Chair from 1981 to 2000. Professor Reddy has published well over six hundred papers in archival journals and the proceedings of international conferences. He received a Von Humboldt Prize in 1995 and the first Life Time Achievement Award from the International Conference on VLSI Design. Professor Reddy is a Life Fellow of IEEE. Professor Reddy has served as associate editor of IEEE Transactions on Computers and IEEE Transactions on CAD.