Cross-Layer Reliability Modeling and Optimization for Embedded Systems under Process Variations

ESWeek 2013

September 29, 2013

Muhammad Shafique, et al.

Muhammad Shafique, Puneet Gupta, Siddharth Garg, Hiren Patel

While advancements in chip manufacturing technology has accelerated the growth of embedded systems, it has revealed serious reliability and robustness challenges at various abstraction levels that threatens the applicability of scaled technologies. With continued miniaturization of feature sizes, engineers are exposed to a variety of vulnerabilities that affect the robustness and reliability of modern embedded systems. These vulnerabilities arise from multiple sources, and result in faults in the hardware that may have catastrophic effects on the correctness of software execution ­­– of particular concern for safety/mission-critical embedded systems. Thus, software abstraction layers cannot make the fundamental assumption that the underlying hardware platform is completely reliable. In order to mitigate the effects of these vulnerabilities, it is critical to develop and design resiliency both in the hardware (device, circuits, and micro-architecture) and software (compilers, operating systems, and programming models). The tutorial provides a comprehensive overview of critical reliability issues and state-of-the-art techniques in detecting and resolving them. Afterwards, the tutorial covers various reliability modeling and optimization techniques at different abstraction layers (i.e. micro-architecture, architecture, compiler, and system/application software). Particular emphasis is placed on the potentials of cross-layer reliability optimization.

Montreal, Canada