IEEE International Symposium on Industrial Embedded Systems (SIES'12)

June 20, 2012

Jörg Henkel

Abstract: As technology scales to 22nm and beyond, reliability becomes a serious concern of densely integrated on-chip systems. Aging effects like electro-migration, NBTI (Negative Bias Temperature Instability), TDDB (Time Dependent Dielectric Breakdown) and other effects alter the electric characteristics of circuits and lead finally to transient and/or permanent faults. High temperature often accelerates these effects and can be seen as a trigger for many known aging effects. But not only aging effects, also various kinds of particle strikes jeopardize reliability as CMOS technology scales to deep nano-scale. In fact, particle strikes may lead to transient bit-flips. All these effects are already observed today and will worsen with each upcoming technology node. So far, mostly physical-level and device-level techniques have been applied to control these negative effects that represent a major hurdle for further technology scaling. However, also architectural-level techniques have been successfully applied. Going even a step further up, we propose to include the whole software stack all the way up to the applications software to control these negative effects. We will show means in form of a few basic software transformations that can contribute to increase reliability in deep nano-scale systems. We emphasize the potential of cross-layer approaches and contribute to the paradigm "Reliable Software for Unreliable Hardware: Embedded Code Generation aiming at Reliability"

Karlsruhe, Germany

2012

• SIES'12