Mini-Workshop Hamburg

  • Name:

    Mini-Workshop Hamburg

  • Venue:

    Hotel Panorama, Hamburg-Harburg

  • Date:

    September 27th

  • Project Leader:

    Prof. Hans-Joachim Wunderlich, Uni Stuttgart

  • Topic:Zuverlaessigkeit und Entwurf (ZUE)
  • we would like to kindly invite you to two SPP-related tutorials on September 27 in Hamburg. The tutorials are co-located with the conference "Zuverlaessigkeit und Entwurf (ZUE)."


    "Defects, Faults, and Errors – Approaches to Cross-Layer Fault-Tolerance"
    Tutorial Workshop in the frame of the DFG Schwerpunktprogramm 1500:
    Dependability of Embedded Systems

    As VLSI fabrication technologies progress further into the nanometer scale, known and new defect mechanisms of semiconductors not only appear during the manufacturing phase, but may occur during the operation of systems and impair their function in the field. These reliability failures processes manifest themselves as temporary or permanent faults during the lifetime of the system.
    Without proper estimation of their impact and according counter-measures at appropriate levels, dependability in the field and lifetime of the system may be significantly reduced. This tutorial presents an introduction to relevant VLSI defect mechanisms, their manifestation and modeling at the appropriate abstraction level. Efficient counter-measures typically exploit time, information, structural redundancy or a combination thereof, to tolerate, detect or correct impaired behavior. The discussed methods are applied at electrical, gate and RT level, up to software and system level.

    M. B. Tahoori (Karlsruher Institut für Technologie), H.-J. Wunderlich (Universität Stuttgart)


    Lunch break


    "Technology Trends in VLSI and Impact on Reliability and Test"

    As technology continues to scale in the nanoscale regime, it's the same physics that helped you in the past, now poses major challenges in design, reliabil- ity, and test. Future designs will have to compre- hend them, and incorporate reliability and test into the design from day one. Traditional system level reliability techniques will be ill suited and will have to morph towards resiliency. This course will address all of these challenges.

    S. Borkar, Intel Corporation, USA


    A summary of the two presentations is attached below for your convenience. More information on ZUE 2011 can be found at


    The registration fee for both tutorials and lunch is 100 Euro and will be refunded by the SPP.

    We are looking forward to your visit!

  • Year: