For more than four decades Moore’s Law has provided a steady exponential grow where each new technology node provided a win-win situation as shrinking features sizes not only led to more complex circuits but also led to faster and less expensive embedded on-chip systems. As Moore’s Law approaches physical limits, though, reliability becomes a severe problem: aging effects like electro migration, NBTI, increased susceptibility against soft errors etc. increasingly jeopardize reliability. So far, mostly physical-level and device-level techniques have been applied to control these negative effects that represent a major hurdle for further technology scaling. However, also architectural-level techniques have been successfully applied. Going even a step further up, we propose to include the whole software stack all the way up to the applications software to control these negative effects. We will show means in form of a few basic software transformations that can contribute to increase reliability in deep nano-scale systems. We emphasize the potential of cross-layer approaches and contribute to the paradigm "Reliable Software for Unreliable Hardware: Embedded Code Generation aiming at Reliability"