Project

Project
Project Leader:

Prof. Samarjit Chakraborty, TU München

Prof. Ulf Schlichtmann, TU München

Topic:Lifting Device-Level Characteristics for Error Resilient System Level Design: A Crosslayer Approach

The rapid shrinking of device geometries in the nanometer regime has led to the need for new design methodologies at various levels of abstraction. While there has been a considerable amount of research at the circuit and gate level – in terms of modeling both manufacturing variabilities and soft errors – not much has been done at the software and system level. Further, existing work on estimating the influence of device-level errors at the software level relies on simulation and artificially injecting various faults. In this project we propose to close this gap between device and software level error resiliency methods and develop a holistic approach to error resilient system design. Towards this, we plan to cut across all levels of design abstraction and in particular lift device-level analysis results to the software and system level. Our methods will help to uncover the effects of bit error probabilities (determined from device characteristics) at the software and higher levels. The main challenges involved in such a cross-layer approach include developing (i) abstraction techniques for propagating device characteristics upwards, (ii) compiler and program analysis techniques to exploit these char- acteristics, (iii) runtime monitoring techniques (e.g., to detect late glitches) to trigger software-level error correction (e.g., repeat particular instructions), and (iv) reliability-aware instruction set simulators. Our work will impact both software design and application-specific circuit design.